The NS9210/NS9215 processor family offers a cost-efficient, small-footprint 32-bit ARM9 solution that combines high performance, integrated Ethernet networking, strong security, and unique interface flexibility. It is the ideal choice for a broad range of applications such as security/access control, medical, industrial/building automation, transportation and remote monitoring. Two independent Flexible Interface Modules (FIMs) with 300 MHz DRPIC1655X processor cores provide a growing list of application-specific peripheral interface options. The NIST-compliant 256-bit hardware AES accelerator combines state-of-the-art data privacy services with superior performance, and Digi’s patented dynamic power management addresses the needs of today’s power budget-conscious designs. The complete and easy-to-use development kits for NET+OS® are based on the field-proven ThreadX® Real-Time Operating System and deliver a true and IPv6-ready turnkey embedded development solution with the Eclipse-based Digi ESP™ IDE.
Platform
NS9210
NS9215
General
Processor
ARM926EJ-S
Speed Grades
75/150 MHz
Cache
4 KB I-cache / 4 KB D-cache
Process
0.18µ CMOS
32-bit ARMv5TEJ Instruction Set
•
16-bit Thumb Instruction Set
•
MMU
•
DSP Instruction Extensions
•
(Improved divide, Single cycle multiply accumulate)
ARM Jazelle® Java Accelerator
•
Embedded ICE-RT Debug Unit
•
JTAG Boundary Scan, BSDL
•
Power Management Modes
•
AES Accelerator
Key Length
128-, 192-, 256-bit
Cipher Modes
ECB, CBC, OFB, CTR, CCM
Hardware Key Expander
•
DMA-Enabled
•
NIST-Compliant
•
FIM (Flexible Interface Module)
FIMs
1/2; Availability depending on application-specific use of
external 16-/32-bit memory bus
2
Cores
8-bit DRPIC1655X
Speed
Up to 300 MHz (4x bus speed)
Data Memory (SRAM)
192 Bytes
Program Memory (SRAM)
2 KB
Interface Options
SD/SDIO, UART, 1-Wire, CAN, USB device (low-speed), Other; Please contact us for custom interface implementation options
Power Management
Dynamic Clock Scaling (patent pending)
Full, /2, /4, /8, /16 speeds, with hardware clock scale control (wake-up events)
Low-Power Sleep Modes
•
Configurable Wake-Up Conditions
External IRQ, I2
C, SPI, UART, Ethernet
External IRQ, I2
C, SPI, UART, Ethernet, RTC
Disabling of Unused System Modules
•
Memory Controller
Glue-less Interface
•
(SDRAM, SRAM, Buffered DIMM, EEPROM, Flash)
Self-Refresh (Sleep Mode)
•
Dynamic/Static Memory Chip Selects
Selection of 5
4/4
Wait States Per Memory Chip Select
0-32
Static Memory Controller Extended Waits (EW)
Up to 16,368
Automatic Dynamic Bus Sizing
•
Burst Support
8-transfer, with automatic data width adjustment
External DMA Channels
2
System Bus DMA
High-Speed Rotating AHB arbiter
16 channels
Deterministic Bus Bandwidth Allocation
•
Multiple Bus Masters
Ethernet Tx/Rx, I/O Hub, Ext DMA, ARM core
External DMA
Independent DMA Channels
2
Transfer Modes
External peripherals, External memory, AHB peripherals
AES DMA Support
•
AHB Master
•
I/O Hub
Low Latency
•
DMA
8 channels
DMA or Direct Access Mode
UART, SPI, FIM
UART, SPI, ADC, FIM
Direct Access Mode Only
I2 C
I2 C , RTC
AHB Master
•
External Interrupts
External Programmable Interrupts
4
Advanced Vectored Interrupt Controller
Two-Tier Priority
•
(FIRQ/IRQ)
Low-Latency FIRQ
•
Interrupt Sources
32
Ethernet MAC
Data Rates
10 / 100 Mbit/s
Duplex
Full and Half
PHY Interface
MII
Address Filtering
Station, Broadcast, Multicast
FIFO
Features
High-performance 150 MHz ARM926EJ-S core 10/100 Mbit Ethernet MAC integration On-chip hardware AES accelerator Software-configurable I/O flexibility through FIMs Power management modes with dynamic clock scaling Rich set of integrated peripheral interfaces Complete and royalty-free NET+OS development platform for network-enabled embedded devices Upgrade path to ARM9 core performance for existing NS7520 designs through pin-compatible NS9210
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